1. Field of the Invention
The present invention relates to a liquid crystal display provided with a thin film transistor array substrate for use in matrix type display and to a manufacturing method thereof.
2. Description of the Prior Art
Generally, a matrix type display comprises a thin film transistor array substrate (hereinafter referred to as TFT array substrate) on which a thin film transistor (hereinafter referred to as TFT) is formed, and a counter substrate on which color filter, black matrix, etc. are formed. A display material such as liquid crystal is held between the mentioned two substrates, and in which a voltage is selectively applied to the display material.
In the TFT array substrate, as shown in the equivalent circuit of FIG. 14, pixels are arranged forming a matrix.
In FIG. 14, reference numerals G1, G2, G3 indicate scanning signal lines (hereinafter referred to as gate lines), and numerals S1, S2, S3 indicate image signal lines (hereinafter referred to as source lines). Cs1, Cs2, Cs3 indicate storage capacitance electrode lines for forming a storage capacitance (hereinafter referred to as Cs lines).
Further, numerals 1a to 1i indicate TFT(s), and charge and discharge of an electric charge to and from a pixel electrode is controlled using the TFT(s) as switching element(s). Numerals 2a to 2i are storage capacitances which are prepared by forming an insulating film between the pixel electrode and the Cs lines. The pixel electrode is formed to be a transparent electrode such as ITO, and forms liquid crystal capacities 3a to 3i holding a liquid crystal between itself and the counter electrode. Numerals 4a to 4i are parasitic capacities Cdp formed parasitically between the source lines and the pixel electrode. On/Off operation of the TFT is performed using the gate lines as gate electrodes.
The pixel electrode is connected to the source line through the TFT, and amount of electric charge given to the pixel electrode varies depending on signal level of the source line, whereby a potential of the pixel electrode is established. In response to a voltage between the pixel electrode and the counter electrode, amount of displacement of liquid crystal varies, and amount of a transmitted light through the backside is changed. Accordingly, by controlling the signal level of the source line, optical signal change is restrained and displayed in the form of an image.
To improve image quality, it is necessary to reduce as small as possible variation in pixel potential due to change in signal level of the gate line, etc. For that purpose, total capacity of the pixel is increased by providing the pixel electrode with the storage capacitances 2a to 2i. The storage capacitances 2a to 2i are formed by providing an insulating film between the Cs lines Cs1 to Cs3 of the same potential as that of the counter electrode and the pixel electrode.
FIG. 15 shows a pixel layout in the conventional TFT array substrate. FIG. 16 shows a sectional view of a region Axe2x80x94A of FIG. 15 taken in the direction of the arrows. FIGS. 17 and 18 show a conventional method of forming a pixel section taking the sectional view of the Axe2x80x94A region as an example.
In FIG. 15, reference numeral 102 indicates a gate line, numeral 104 indicates a semiconductor thin film, numeral 107 is a source line, numeral 108 is a source electrode, numeral 109 is a drain electrode, numeral 111 is a Cs line, and numeral 114 is a pixel electrode.
In FIG. 16, reference numeral 101 indicates a glass substrate, and numeral 103 indicates a gate insulating film, numeral 105 is an i-layer (a semiconductor layer composed of non-doped amorphous silicon, etc.). Numeral 106 is a n-layer (for example, a semiconductor layer composed of amorphous silicon, etc. containing n-type impurity), and numeral 113 is an insulating film. Same reference numerals as those given for the above description are designated to the same or like parts.
A manufacturing process of the matrix type display having a sectional structure as shown in FIG. 16 is hereinafter described with reference to FIGS. 17 and 18.
First, as shown in FIG. 17(a), a metal film 102a to serve as the gate electrode 102 is formed on the glass substrate 101, and then, as shown in FIG. 17(b), a resist pattern 110a having a planar shape corresponding to the gate electrode 102 is formed thereon. Using the resist pattern 110a as an etching mask, an etching is applied to the metal film 102a, thus the gate electrode 102 is obtained, and then the resist pattern 110a is removed.
Then, as shown in FIG. 17(c), the gate insulating film 103, i-layer 105, and n-layer 106 are laminated in order, and as shown in FIG. 17(d), a resist pattern 110b is formed on the region where the i-layer 105 and the n-layer 106 are left, and using the resist pattern 110b as an etching mask, the n-layer 106 and the i-layer 105 are etched in order. The resist pattern 110b is then removed.
Subsequently, as shown in FIG. 17(e), an ITO thin film 114a to serve as the pixel electrode 114 is further placed, and as shown in FIG. 18(a), using a resist pattern 110c patterned into a shape corresponding to the pixel electrode 114 as an etching mask, the pixel electrode 114 is obtained by etching the ITO thin film 114a. The resist pattern 110c is then removed.
Then, as shown in FIG. 18(b), a metal film 112a to serve as source line 107, source electrode 108, and drain electrode 109 is placed. And as shown in FIG. 18(c), a resist pattern 110d corresponding to a region required to serve as source line 107, source electrode 108 and drain electrode 109, is patterned. Using the resist pattern 110d as an etching mask, the metal film 112a is etched, then the resist pattern 110d is removed, whereby the insulating film 113 is formed. As a result, a conventional matrix type display of the sectional structure shown in FIG. 16 is obtained.
Then, structure and function of the conventional TFT is hereinafter described. With reference to the mentioned FIG. 16, when the pixel electrode 114 is charged with an electric charge, a voltage of about 9V is applied to the source electrode 108, and a positive voltage of about 20V is applied to the gate. electrode 102, whereby the TFT is turned on, and the drain electrode 109 and the pixel electrode 114 are charged approximately to 9V.
Thereafter, when potential of the pixel electrode 114 has sufficiently increased, a negative voltage of about xe2x88x925V is applied to the gate electrode 102, whereby the TFT is turned off, and the electric charge is constrained in the pixel.
In the conventional pixel structure described above, the pixel electrode 114 is connected to the source line 107 through the TFT, and potential of the pixel electrode 114 is established depending on signal level of the source line 107. In response to the voltage between the pixel electrode 114 and the counter electrode, amount of displacement of the liquid crystal varies and the transmitted light from the backside is changed.
Accordingly, by controlling signal level of the source line 107, optical signal change is controlled and displayed in the form of an image.
Maximum brightness of the liquid crystal display is determined by light transmittance (transmissivity of light) in the mentioned pixel, and the light transmittance becomes higher when area of the part through which light is transmitted, i.e., aperture in the pixel is larger. To achieve a liquid crystal display of high brightness, it is necessary to increase the area of aperture occupied in the area of the entire pixel (hereinafter referred to as aperture ratio).
As a method for increasing the aperture ratio, it is useful to decrease the distance between the pixel electrode 114 and the source line 107 in FIG. 15. However, when decreasing the distance between the pixel electrode 114 and the source line 107, the parasitic capacity Cdp generated between the source line 107 and the pixel electrode 114 in FIG. 14 is increased.
Generally, when varying the source signal, the pixel potential is changed through the parasitic capacity Cdp. Variation in the pixel potential becomes larger, when the parasitic capacity Cdp is larger and variation in the source signal is larger. When the parasitic capacity Cdp becomes large, a problem of crosstalk occurs. This problem of crosstalk is hereinafter described with reference to FIG. 14. The crosstalk is a phenomenon that, when amplitude of the source signal is increased only for writing data in the pixel (liquid crystal capacity 3a) and amplitude of the source signal is decreased for writing data in the other pixels (liquid crystal capacities 3b to 3i), potential of the pixel having liquid crystal capacities 3d, 3g on the source line S1 is changed by the increased source signal amplitude for writing data in the pixel and having the liquid crystal capacity 3d, and the pixel potential is different from the adjacent pixel having liquid crystal capacities 3e, 3h. 
In this crosstalk, the pixels other than that having the liquid crystal capacity 3a should be of same display data and same brightness, but there arises a difference in brightness between the pixel on the source line S1 and the pixels on the source lines S2, S3. In other words, there arises a problem that, as the crosstalk occurs when decreasing the distance between the pixel electrode 114 and the source line 107, it is necessary to secure a distance exceeding a certain value between the pixel electrode and the source line. As a result, aperture ratio of the liquid crystal display cannot be increased.
The Japanese Laid-Open Patent Publication (unexamined) 288824/1991 disclosed one of the prior arts. This patent publication shows a liquid crystal display in which a line corresponding to the Cs line and the pixel electrode are partially overlapped.
As discussed above, in the pixel structure of the conventional TFT array substrate, there is a problem that when decreasing the distance between the pixel electrode and the source line to improve the aperture ratio, the parasitic capacity Cdp is increased, eventually resulting in occurrence of crosstalk.
Further, in the array substrate of the conventional active matrix type liquid crystal display, to form an array, a plurality of gate lines are arranged in row and a plurality of source lines are arranged in train on an insulating substrate. Further, a TFT and one pixel composed of a pixel electrode connected to the TFT are formed at a crossover position of each gate line and each source line, and an orientation film is formed thereon.
On the other hand, in the counter substrate being another substrate for holding the liquid crystal, a common electrode is formed on the insulating substrate, and an orientation film is formed thereon. Surfaces of the array substrate and the counter substrate on which the pixel electrode and the common electrode are formed are put facing to each other, and a liquid crystal composite is held in a gap between the two substrates. Usually, as the orientation film is oriented in a direction displaced by 90 degrees between the array substrate side and the counter substrate side, a TN liquid crystal in which liquid crystal particles are arranged twisted by 90 degrees in the direction of thickness is used.
FIG. 19 is a plan view showing a pixel of another conventional TN type liquid crystal display disclosed in the Japanese Laid-Open Patent Publication (unexamined) 308533/1994.
In the drawing, reference numeral 201 indicates a source line, numeral 202 indicates a gate line arranged to crossover the source line 201, and numeral 203 is a Cs line forming a storage capacitance which is formed by the same process as the gate line 202. Numeral 204 is a semiconductor layer forming a channel of the TFT, numeral 205 is a pixel electrode, and numeral 206 is a drain electrode of the TFT connected to the pixel electrode 205. The TFT is formed of the semiconductor layer 204, source line 201, gate line 202 and drain electrode 206.
FIG. 20 is a schematic diagram showing a signal flow at the time of interrupting the Cs line of the pixel of the conventional liquid crystal display.
In the drawing, reference numeral 208 indicates a short circuit point between the gate line 202 and the Cs line 203. Numeral 209 is two interrupting points for interrupting the Cs line 203 on two sides of the short circuit point 208, and numeral 210 indicates a signal flow of the Cs line 203. Sn is a source line, Gk is a gate line, and Vcom is a potential of the common electrode of the counter substrate. Potential of the Cs line is equal to that of the common electrode.
Operation of the conventional liquid crystal display of above arrangement is hereinafter described.
When an on signal is applied to the gate line 202, the TFT is turned on, and a predetermined electric charge is written from the source line 201 in the storage capacitance and the capacity of liquid crystal (hereinafter referred to as Clc). Then, when the selective signal of the gate line 202 is turned off, the TFT is turned off (a high resistance state), and the electric charge written from the source line is held. An effective voltage determined by the difference between the potential determined by this electric charge and the potential of the common electrode of the counter substrate is applied to the liquid crystal, whereby a light transmittance in proportion to the effective voltage is obtained. As a result, a desired display is achieved.
At this time, when varying the selective signal of the gate line 202, potential of the drain electrode 206 is changed by a coupling capacity Cgd of the gate line 202 and the drain electrode 206. Supposing that the potential variation is xcex94Vgd, the xcex94Vgd is shown in the following expression:
xcex94Vgd=(Cgdxc3x97xcex94Vg)/(Cgd+Cs+Clc)xe2x80x83xe2x80x83(1)
where: xcex94Vg is a variation of potential when the signal from the gate line 202 is turned from on to off. Because of the variation xcex94Vgd of the potential of the drain electrode 206, the central potential of the potential Vcom of the common electrode of the counter substrate and the central voltage of the voltage applied to the liquid crystal are displaced. It is well known that if the variation is large, there arises a flicker in image plane, and a phenomenon (hereinafter referred to printing) takes place in which when a pattern is continuously displayed for a long time, the same pattern still remains after being switched to the other pattern, which results in deterioration of display quality. To prevent such problem, it is necessary to add a predetermined storage capacitance in parallel to the liquid crystal capacity.
On the other hand, in the liquid crystal display, the light transmitted through the part other than the pixel electrode 205 brings about a disadvantage of deterioration of display quality such as lowering in contrast ratio. Accordingly, it is necessary to shade any leak of light transmitted through the part other than the pixel electrode 205. In the conventional liquid crystal display, leak of light from the gap between the pixel electrode 205 and the source line 201 is shaded by arranging the Cs line 203 in the periphery of the pixel electrode to form a shade film. In such a case, the Cs line 203 is located in the periphery of the pixel electrode along the source line 201, extending to the part near the gate line 202. In this respect, as compared with the case of forming a shade film on the array substrate, when shading the leak light by the shade film arranged on the counter substrate, alignment accuracy of the counter substrate and the array substrate is lower than the pattern accuracy of the array substrate, resulting in a large shading region. Accordingly, when the gap between the gate line 202 and the Cs line 203 serving as the shade film is formed as small as possible, the shading region by the shade film arranged on the counter substrate is reduced, and aperture ratio is improved.
In the conventional liquid crystal display of above arrangement, the Cs line 203 performs a function of shading the leak light out of the gap between the pixel electrode 205 and the source line 201, and the Cs line 203 is located near the gate line 202. Because the gate line 202 and the Cs line 203 are formed in the same process, there arises a defect of short circuit between the gate line 202 and the Cs line 203 due to defective pattern such as foreign matter stuck at the time of photomechanical process and etching. When occurs such a defect of short circuit, any scanning signal is not supplied normally, which is visually recognized as defective line. Such a defective line can be detected by the inspection after completing the manufacturing process of the array substrate, and it is possible to cut the defect with a laser or the like. However, in the event that such a defect of short circuit takes place under the source line 201, a problem exists in that when interrupting the short circuit portion, the source line 201 is also interrupted and visually recognized as defective source line, making it impossible to repair the defect.
Moreover, it is certainly possible to cut the Cs line 203 at the two interruption points 209 on both sides of the short circuit point 208 as shown in FIG. 20. But, in this case, the signal supplied to the Cs line 203 is supplied from one side of the image plane. For example, in the event of interrupting the Cs line 203 in response to a short circuit between the gate line 202 and the Cs line 203 near the right end of the image plane, the signal supplied to the Cs line 203 is supplied from the left end side of the image plane. Therefore, a load on the Cs line 203 is four times as much as the normal supply, and a signal delay occurs. Due to such a signal delay, brightness varies as compared with peripheral pixel, and the Cs line 203 is visually recognized as defective line that is another problem.
Accordingly, an object of the present invention is to provide a TFT-LCD (LCD is an abbreviation of liquid crystal display) of high quality in which parasitic capacity Cdp hardly increases and crosstalk is small by arranging a pixel electrode on a source line through a Cs line.
Another object of the invention is to provide a TFT-LCD of high aperture ratio and high brightness by forming a pixel electrode extending to a source line through a Cs line.
A further object of the invention is to provide a liquid crystal display of high yield.
A still further object of the invention is to provide a manufacturing method of a liquid crystal display conforming to each of the foregoing objects.
A liquid crystal display according to the present invention comprises a TFT array substrate for use in matrix type display, the TFT array substrate including a plurality of gate lines arranged on an insulating substrate with certain distances, a plurality of source lines crossing over the gate lines, and TFT(s) provided at crossover sections between the gate lines and the source lines, and having pixel electrodes connected to drain electrodes forming the TFT(s), and Cs lines each forming a storage capacitance by holding an insulating film between the Cs lines and pixel electrodes, wherein the Cs lines are arranged and formed in such a manner as to overlap an upper part of the source lines.
In the liquid crystal display according to the invention, it is preferable that the Cs lines are formed into a mesh-like structure having line components in wiring direction of the source lines and the gate lines, in addition to the mentioned construction.
In the liquid crystal display according to the invention, it is preferable that the pixel electrodes are arranged and formed in such a manner as to overlap an upper layer of the Cs lines, in addition to the mentioned construction.
In the liquid crystal display according to the invention, it is preferable that the line component in wiring direction of the source lines is formed to be wider than the source lines in such a manner as to cover the source lines, in addition to the mentioned construction.
In the liquid crystal display according to the invention, it is preferable that the Cs lines are arranged in such a manner as to extend in one direction along the source lines and formed to be wider than the source lines in such a manner as to cover the source lines, and the pixel electrodes are arranged and formed in such a manner as to overlap the upper layer of the Cs lines, in addition to the mentioned construction.
In the liquid crystal display according to the invention, it is preferable that the pixel electrodes and the gate lines overlaps partially each other, in addition to the mentioned construction.
A manufacturing method of a liquid crystal display according to the invention comprises the steps of forming source lines, Cs lines and pixel electrodes in order, and arranging the source lines, Cs lines and the pixel electrodes in such a manner that they overlap partially one another.
A liquid crystal display according to the invention comprises pixel electrodes respectively formed in a plurality of matrix-like regions defined by a plurality of gate lines and a plurality of source lines arranged in such a manner as to cross over said gate lines, and Cs lines arranged in such a manner as to extend over the plurality of regions along the gate lines, wherein the Cs lines are arranged in such a manner that two Cs lines extend within each region, and the two Cs lines are connected to each other within a part of the regions.
In the liquid crystal display according to the invention, it is preferable that the Cs lines have a wiring section shaped to shade a leak light from between the pixel electrodes and the source lines.
In the liquid crystal display according to the invention, it is preferable that the Cs lines are connected through the wiring section in the region where the Cs lines are connected to each other.
In the liquid crystal display according to the invention, it is preferable that the two Cs lines are connected to each other at least within two regions.
In the liquid crystal display according to the invention, it is preferable that the regions in which the two Cs lines are connected to each other are arranged with equal distances.
In the liquid crystal display according to the invention, it is preferable that the gate lines and the Cs lines are formed into a same layer.
A manufacturing method of a liquid crystal display according to the invention comprises a first step of arranging Cs lines along gate lines in such a manner that two Cs lines extend within a region and forming the gate lines and the Cs lines in such a manner that the two Cs lines are connected to each other within a part of the regions, and a second step of forming source lines in such a manner as to cross over the gate lines through an insulating film.
In the manufacturing method of a liquid crystal display according to the invention, it is preferable that when a gate line and a Cs line short-circuits under a signal line, the Cs line is interrupted on two sides of the source line.